Shallow trench isolation using antireflection layer

ABSTRACT

Shallow trench isolation among transistors and other devices on a semiconductor substrate is provided by initially forming a plurality of light absorbing layers having a combined extinction coefficient &gt;0.5. As reflected light passes through the light absorbing layers, a substantially amount of light is absorbed therein thereby blocking such reflected light from negatively interfering with patterning of the photoresist during photo-lithography. Following patterning of the photoresist, isolation trenches are formed in the semiconductor substrate by etching through the light absorbing layers and into the semiconductor substrate in accordance with the pattern formed on the photoresist.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a divisional of, and claims priority under 35U.S.C. §120 to, U.S. application Ser. No. 09/861,990, filed May 17,2001, now U.S. Pat. No. 6,645,868, which in turn is a divisional of, andclaims priority under 35 U.S.C. §120 to U.S. application Ser. No.09/200,307, filed Nov. 25, 1998, now U.S. Pat. No. 6,255,717, issued onJul. 3, 2001.

TECHNICAL FIELD

The present invention relates to a method for forming isolation regionsamong devices on a semiconductor substrate, and more particularly, to amethod of patterning photoresist to form such isolation regions withreduced effects from photo-reflectivity.

BACKGROUND OF THE INVENTION

In the semiconductor industry, there is a continuing trend toward higherdevice densities. To achieve these high densities there has been andcontinues to be efforts toward scaling down the device dimensions onsemiconductor wafers. In order to accomplish such high device packingdensity, smaller and smaller features sizes are required. This mayinclude the width and spacing of interconnecting lines and the surfacegeometry such as corners and edges of various features.

The requirement of small features with close spacing between adjacentfeatures requires high resolution photolithographic processes. Ingeneral, lithography refers to processes for pattern transfer betweenvarious media. It is a technique used for integrated circuit fabricationin which a silicon slice, the wafer, is coated uniformly with aradiation-sensitive film, the resist, and an exposing source (such aslight, x-rays, or an electron beam) illuminates selected areas of thesurface through an intervening master template, the mask, for aparticular pattern. The lithographic coating is generally aradiation-sensitized coating suitable for receiving a projected image ofthe subject pattern. Once the image is projected and developed, it isindelibly formed in the coating.

One important aspect of producing an integrated circuit involves theisolation of devices that are built on a semiconductor substrate of awafer. For instance, isolation becomes extremely important in integratedcircuit technology as many hundreds of thousands of devices are producedin a single chip. Improper isolation among transistors may cause currentleakages, which can consume significant power for the entire chip.Further, improper isolation can lead to increased noise among devices onthe chip.

One known way of isolating devices built on a semiconductor chipinvolves local oxidation of silicon (LOCOS). LOCOS involves growingsilicon dioxide by heating an exposed area of silicon (or siliconcovered with a thin layer of silicon dioxide) in an oxygen containingambient. Prior to LOCOS growth, a wafer will normally be covered with aninert layer of material, such as silicon nitride (Si₃N₄), and thenitride layer is patterned to expose the areas selected for LOCOSformation. The localized regions of oxide are then grown in the exposedareas, and the silicon nitride layer is then removed.

Another way of isolating devices built on a semiconductor chip is toform isolation regions between neighboring devices. For instance, usinga shallow trench isolation technique, shallow trenches are formedbetween devices on the semiconductor chip so that a dielectric layersuch as silicon oxide may be formed therein to electrically isolateadjacent devices. In order to produce the shallow trenches, a barrieroxide layer is typically formed over a semiconductor substrate, and asilicon nitride layer is formed over the barrier oxide layer. Next, aphotoresist is patterned over the silicon nitride layer to serve as amask when forming the shallow trench. Using the photoresist, the shallowtrench is formed through the layers into the semiconductor substrate andis filled with the dielectric material. The photoresist and siliconoxide layer are subsequently removed using conventional techniques.

During any lithographic/etching process such as that involved in formingthe shallow trench isolation regions, it is extremely important tocontrol critical dimensions (CDs) such as linewidth and spacing of thephotoresist. Unfortunately, the use of highly reflective materials suchas metal silicides in photolithography has lead to difficulties inmaintaining tight CD control. In particular, undesired and nonuniformreflections from these underlying materials during the photoresistpatterning process often causes the resulting photoresist patterns to bedistorted. Because the photoresist patterns are used as a mask informing the shallow isolation trenches, such distortions have acorresponding negative impact on the CD control of these trenches.

Distortion in the photoresist are further created during passage ofreflected light through a silicon nitride layer Si₃N₄ which is used as ahardmask for shallow trench isolation etching. As is conventional, thehardmask serves to provide an additional mask layer for forming theshallow trenches in the event the softer photoresist material becomeseroded prior to or during the isolation trench forming steps. Duringmanufacturing of the semiconductor chip, however, normal fluctuations inthe thickness of the hardmask cause a wide range of varying reflectivitycharacteristics across the silicon nitride layer. As a result,maintaining tight CD control of the photoresist pattern and ultimatelythe isolation trenches is difficult.

A known method for reducing the negative effects resulting from thereflective materials used in forming a semiconductor chip includes theuse of anti-reflective coatings (ARCs). For example, one type of ARC isa polymer film that is formed between the photoresist and thesemiconductor substrate. The ARC serves to absorb most of the radiationthat penetrates the resist (70-85%) thereby reducing the negativeeffects stemming from the underlying reflective materials duringphotoresist patterning. Unfortunately, use of an ARC adds significantdrawbacks with respect to process complexity. For instance, in order toutilize an organic or inorganic ARC, the process of manufacturing thesemiconductor chip must include a process step for depositing the ARCmaterial, and also a step for prebaking the ARC before spinning thephotoresist.

Accordingly, there exists a need in the art for a method of forming aresist pattern for shallow trench isolation which overcomes thedrawbacks described above and others.

SUMMARY OF THE INVENTION

The present invention provides a method for forming shallow trenchisolation among transistors and other devices on a semiconductorsubstrate with tight critical dimension (CD) control. Tight criticaldimension control is achieved by virtue of including a highly absorbinglayer of silicon rich nitride as a hardmask between a photoresist and abarrier oxide layer disposed on a semiconductor substrate. The highlyabsorbing layer of silicon rich nitride has an extinction coefficient(k)>0.5. As such, not only is the amount of reflectivity reduced butalso the variance in reflectivity caused by thickness variations in theconventional silicon nitride layer which adversely affected photoresistpatterning is significantly reduced. Also, the manufacturing process issimplified since forming of the silicon nitride layer serves as both ahardmask and an anti-reflective layer and thus no additionalmanufacturing step is needed to deposit an additional anti-reflectivecoating. In other words by using a silicon rich nitride layer as ahardmask, the cycle time for manufacturing each wafer is reduced sinceless manufacturing steps are needed.

Alternatively, rather than including a layer of silicon rich nitride,multiple alternating layers of SiON and SiO₂ may be stacked between thesemiconductor substrate and the photoresist to achieve substantially thesame affects of reduced reflectivity and reduced variance inreflectivity. The number of layers and thickness of each layer of SiONand SiO₂ is such that collectively the reflectivity of light during thephoto-lithography process does not negatively impact the criticaldimensions of the photoresist pattern. Thus, for example, the collectivelayers of SiON and SiO₂ may be such as to provide an extinctioncoefficient in which k>0.5.

Thus, according to one aspect of the present invention, aphotolithographic method for forming isolation trenches is provided. Thephotolithographic method includes the steps of forming a silicon richnitride layer over a semiconductor substrate, the silicon rich nitridelayer having an extinction coefficient >0.5, patterning a photoresistover the silicon rich nitride layer, and etching a plurality ofisolation trenches through said silicon rich nitride layer into saidsemiconductor substrate.

In accordance with another aspect of the present invention, aphotolithographic method for forming isolation trenches is provided. Thephotolithographic method includes the steps of forming a plurality oflight absorbing layers having a combined extinction coefficient >0.5over a semiconductor substrate, the light absorbing layers alternatingbetween a layer of SiON and a layer of SiO₂, patterning a photoresistover the plurality of light absorbing layers, and etching a plurality ofisolation trenches through the plurality of light absorbing layers intosaid semiconductor substrate

In accordance with yet another aspect of the present invention, a filmstack used in forming shallow trench isolation among integrated circuitcomponents on a wafer is provided. The film stack includes asemiconductor substrate, a silicon rich nitride layer disposed over thesemiconductor substrate, the silicon rich nitride layer having anextinction coefficient >0.5; and a photoresist disposed over the siliconrich nitride layer.

In accordance with still another aspect of the present invention, aphotolithographic method for pattern transfer is provided. The methodincludes the steps of forming a silicon rich nitride layer over asemiconductor substrate, the silicon rich nitride layer having anextinction coefficient >0.5, patterning a photoresist over the siliconrich nitride layer, and transferring the pattern of the photoresist tothe silicon rich nitride layer.

To the accomplishment of the foregoing and related ends, the inventionthen, comprises the features hereinafter fully described andparticularly pointed out in the claims. The following description andthe annexed drawings set forth in detail certain illustrativeembodiments of the invention. These embodiments are indicative, however,of but a few of the various ways in which the principles of theinvention may be employed and the present invention is intended toinclude all such embodiments and their equivalents. Other objects,advantages and novel features of the invention will become apparent fromthe following detailed description of the invention when considered inconjunction with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the annexed drawings:

FIG. 1 illustrates a partial cross-sectional view of an integratedcircuit wafer during a first process step in forming isolation trenchesin the wafer in which a barrier oxide layer is shown above asemiconductor substrate in accordance with the present invention;

FIG. 2 illustrates a partial cross-sectional view of the wafer of FIG. 1during a second process step in forming isolation trenches in which asilicon rich nitride layer is formed over the barrier oxide layer;

FIG. 3 illustrates a partial cross-sectional view of the wafer of FIG. 2during a third process step in forming isolation trenches in which aphotoresist layer is formed over the silicon rich nitride layer;

FIG. 4 illustrates a partial cross-sectional view of the wafer of FIG. 3during a forth process step in forming isolation trenches in which thephotoresist layer is patterned to form isolation trenches in thesemiconductor substrate;

FIG. 5 illustrates a partial cross-sectional view of the wafer of FIG. 4during a fifth process step in forming isolation trenches in whichtrenches are formed into the semiconductor substrate in accordance withthe patterned photoresist;

FIG. 6 illustrates a partial cross-sectional view of the wafer of FIG. 5during a sixth process step in forming isolation trenches in which thephotoresist layer and silicon rich nitride layers are stripped from thewafer;

FIG. 7 illustrates a partial cross-sectional view of the wafer of FIG. 6during a seventh process step in forming isolation trenches in which adielectric material is formed in the trenches in the semiconductorsubstrate;

FIG. 8 illustrates a partial cross-sectional view of the wafer of FIG. 7during an eighth process step in forming isolation trenches in which thedielectric material is polished to be substantially flush with a topsurface of the semiconductor substrate;

FIG. 9 illustrates a partial cross-sectional view of a wafer accordingto an alternative embodiment of the present invention in which alternatelayers of SiON and SiO₂ are deposited over a semiconductor substrate tocollectively serve to reduce the effects of light reflectivity onphotoresist pattern; and

FIG. 10 illustrates a partial cross-sectional view of the wafer offollowing etching of the silicon rich nitride layer- and barrier oxidelayer just prior to applying LOCOS isolation techniques in accordancewith the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described with respect to theaccompanying drawings in which like numbered elements represent likeparts.

In order to create shallow trench isolation (STI) among componentsdisposed on a wafer with tight critical dimension (CD) control, thepresent invention provides a silicon rich nitride layer to serve as botha hardmask and an anti-reflective layer during the manufacturingprocess. In the present invention, the silicon rich nitride layer has aextinction coefficient (k)>0.5. By forming the hardmask of a siliconrich nitride layer, light which is reflected by the semi-conductorsubstrate and other material during photo-lithographic patterning of thephotoresist substantially is absorbed by the silicon rich nitride layer.Thus, thickness variations in the silicon rich nitride layer do notresult in non-uniform amounts of light being incident on the photoresistwhich in turn could result in distortions during photoresist patterning.

Referring initially to FIG. 1, a first process step in forming isolatingtrenches on a wafer 20 is shown in which a semiconductor substrate 25 iscoated with a barrier oxide layer 30. In the present embodiment, thesubstrate 25 is made of silicon, Si, while the barrier oxide layer 30 ismade of silicon oxide, SiO₂. As is conventional, the barrier oxide layer30 serves to block nitrides from passing to the semiconductor substrateduring the manufacturing process. In the present embodiment the SiO₂ hasa thickness of 150 Å, however it will be appreciated that such thicknessmay be varied depending on the application at hand.

FIG. 2 shows a second process step in forming isolation trenches on thewafer 20 in which a hardmask 35 composed of a silicon rich nitride isformed on the barrier oxide layer 30. In the present embodiment thehardmask 35 is formed of a silicon rich nitride which has an extinctioncoefficient (k)>0.5. In particular, the silicon rich nitride of thehardmask 35 of the present invention has a thickness of 500 Å whichprovides an extinction coefficient of k=0.6. The refractive index of thesilicon rich nitride is approximately 2.3 as measured at a wavelength of230 nm. It will be appreciated that a silicon rich nitride is anysilicon rich nitride having a formula Si_(x)N_(y) where the ratio of Xto Y (i.e. X/Y) is approximately 0.75 or greater. Further, the hardmask35 may vary in thickness preferably in the range of 100-600 Å dependingon the degree of light absorption desired although the thickness may beincreased up to 1800 Å or greater in some applications. As will bediscussed in more detail below, by providing a hardmask 35 composed of asilicon rich nitride having an extinction coefficient of k>0.5, thepresent invention allows for providing tighter critical dimensioncontrol during patterning of a photoresist which in turn leads totighter critical dimension control of the shallow trenches formed in thesubstrate 25. Such tighter critical dimension control is possible sincethe hardmask absorbs a large percentage of reflected light and thus anon-uniform distribution of reflected light which may otherwise beincident on the photoresist during photo-lithography patterning issubstantially absorbed by the hardmask. Further, such tighter criticaldimension control is possible without adding extra manufacturing stepswhich are conventionally necessary to add, for example, a separateanti-reflective coating (ARC) to the wafer 20.

In order to deposit the silicon rich nitride onto the wafer 20, thesilicon rich nitride is deposited in a furnace operating at atemperature of approximately 760° C. The gases used in depositing thesilicon rich nitride in the furnace include dichloro silane (SiCl₂H₂) ata flow rate of 120 standard cubic centimeters per minute (sccm) andamonia (NH₃) at a flow rate of 8 sccm thereby giving a 15:1 ratio ofSiCl₂H₂ to NH₃. The pressure in the furnace is set at 200 m torr.

Referring now to FIG. 3, a third process step in forming isolationtrenches is shown in which a photoresist 40 is formed over the hardmask35. The formation of the photoresist 40 completes a film stack used informing the shallow trench isolation. The photoresist 40 is composed ofa conventional photoresist material which is suitable to be patternedusing photo-lithography. FIG. 4 depicts a fourth process step in formingisolation trenches in which the photoresist 40 is patterned to serve asa mask in forming trenches in the substrate 25. For example, referringto FIG. 4, during photo-lithography a series of photoresist trenches 45(only one shown) are formed in the photoresist 40 to provide a windowthrough which etching of the underlying hardmask 35 and substrate 25 maytake place. Thus, if the critical dimensions, such as a line width andspacing, of the photoresist trenches 45 are not closely controlled,distortions occurring in forming of the photoresist trenches 45 will bepassed down to the isolation trenches ultimately formed in the substrate25. As mentioned above, conventionally such distortions in patterningthe photoresist 40 occurred partly due to thickness variations in thehardmask 35 which caused non-uniform photo-reflectivity and due tovarying degrees of reflectivity occurring from underlying materials suchas the substrate 25 and other electronic components disposed therein.However, as the hardmask 35 of the present invention has a highextinction coefficient wherein k>0.5, the light which passes through theresist 40 tends to be absorbed by the hardmask 35 and the light which isreflected by underlying layers below the hardmask 35 or by the hardmask35 itself is also substantially absorbed within the hardmask 35 prior tobeing reflected back onto the photoresist 40 thereby reducing variationswhich would otherwise occur in the critical dimensions of thephotoresist trenches 45.

Referring now to FIG. 5, a fifth process step in forming isolationtrenches is shown in which a shallow isolation trench 50 is formed inthe substrate. The shallow isolation trench 50 is formed by conventionalplasma etching of the hardmask 35, barrier oxide layer 30 and substrate25. In the present embodiment, the plasm etching of the hardmask35/barrier oxide layer 30 and substrate 25 occurs in two consecutiveplasma etching steps, however, it will be appreciated that plasm etchingof the hardmask 35, barrier oxide layer 30 and substrate 35 could occurin a single step. As seen in FIG. 5, the isolation trench 50 formedduring the plasma etching is trapezoidal in shape and has side walls 55which are angled approximately 70° with respect to a horizontal line. Itwill be appreciated, however, that the isolation trenches 50 may beshaped in other appropriate shapes and the present invention is notlimited to having isolation trenches which are trapezoidal in shape. Thedepth of the isolation trenches 50 may also vary from one application toanother, however in the present embodiment the depth of the isolationtrench 50 is approximately 3500 Å.

Referring now to FIG. 6, a sixth process step in forming isolationtrenches is shown in which the hardmask 35 and photoresist 40 arestripped from the wafer 20. Stripping of photoresist 40 occurs inaccordance with conventional photoresist stripping techniques. Strippingof the hardmask 35 also occurs using conventional techniques such as wetstripping, and in the present embodiment is accomplished usingphosphoric acid as a wet strip solution.

Referring now to FIG. 7, a seventh process step in forming isolationtrenches is shown in which a dielectric material is formed in theisolation trenches 50. In the present embodiment, the dielectricmaterial formed in the isolation trenches 50 is silicon oxide, SiO₂which is formed from a TEOS gas, however other appropriate dielectricmaterials could alternatively be used. The dielectric material serves toelectrically isolate adjacent components on the substrate 25 from oneanother.

Referring now to FIG. 8, following formation of the dielectric material60 in the isolation trenches 50, an eighth and final step of isolatingdevices on the substrate 25 is depicted in which the dielectric material60 formed over the substrate 25 and in the isolation trenches 50 arepolished in order to planarize the entire substrate surface. Followingpolishing, the dielectric material 60 filled in the isolation trenches50 is substantially flush with a top surface 65 of the substrate 25 asshown in FIG. 8. At this point, the formation of the isolation trenches50 in the substrate 25 which are suitable for electrically isolatingadjacent components from one another is completed, and the wafer 20 isprogressed to the next stage in the overall manufacturing process.

As discussed above, because the hardmask 35 of the present invention hasan extinction coefficient wherein k>0.5, the critical dimensions of thephotoresist trenches 45 are not significantly affected by the thicknessvariations in the hardmask 35 or other non-uniformities in reflectedlight. Thus, when patterning the photoresist 40 using a conventionalphoto-lithographic process, the critical dimensions of the photoresisttrenches 45 are not negatively impacted by varying degrees of reflectedlight being incident thereon. Further, because the hardmask 35 itselfserves as an anti-reflective coating, manufacturability of the wafer 20is simplified since no additional process step is needed to form anextra anti-reflective coating on the substrate 25. This in turn leads toa shorter cycle time in manufacturing of wafers 20.

Referring now to FIG. 9, an alternative embodiment of the presentinvention is depicted in which a multilayer stack 75 of light absorbingmaterial is formed over the substrate 25. The multilayer stack 75 iscomposed of alternating layers of SiON 80 and SiO₂ 85 as shown in FIG.9. Each layer of SiON and SiO₂ is preferably between 100 and 400 Å inthickness and in the present invention each layer has a thickness of 250Å. The combined extinction coefficient of the multilayer stack 75 issuch that k>0.5 thereby allowing for patterning of the photoresist 40without a significant negative impact on the critical dimensions of thephotoresist trenches 45 which would otherwise occur from variations inthe intensity of reflected light incident on the photoresist duringphoto-lithography. In the present embodiment the multilayer stack 75includes three light absorbing layer in which two layers of SiON 80sandwich a layer of SiO₂ 85. It will be appreciated, however, that twoor more layers of light absorbing material may be used depending on thedesired amount of light absorption needed for a particular application.

The process of forming an isolation trench 50 in the substrate 25 andfilling the isolation trench 50 with a dielectric material 60 in thepresent embodiment is substantially similar to the steps described abovewith respect to FIGS. 1-8 and with the exception that the multilayerstack 75 is used in place of the hardmask 35. As such, the process offorming the isolation trench 50 is not again shown for sake of brevity.

The invention has been described with reference to the preferredembodiments. Obviously, modifications and alterations will occur toothers upon reading and understanding the preceding detaileddescription. For example, although the present invention has beendescribed with respect to patterning a photoresist for forming shallowtrench isolation among components on a wafer, the present invention mayalso be used in conjunction with contact patterning, via patterning,damascene and/or LOCOS. In particular, briefly referring to FIG. 10, inthe event the present invention was used in conjunction with LOCOS, thebarrier oxide layer 30 and hardmask 35 would be patterned and etched insubstantially the same manner as described above with respect to FIGS.1-5 except that the substrate 25 would not be etched to form isolationtrenches 50. Rather, once the hardmask 32 and oxide layer 30 are etched,conventional LOCOS techniques would be used to grow an oxide withinregions 100. It is intended that the invention be construed as includingall such modifications alterations, and equivalents thereof and islimited only by the scope of the following claims.

What is claimed is:
 1. A photolithographic method for forming isolationtrenches, comprising the steps of: forming a plurality of lightabsorbing layers having a combined extinction coefficient >0.5 over asemiconductor substrate, the light absorbing layers alternating betweena layer of SiON and a layer of SiO₂; patterning a photoresist over theplurality of light absorbing layers; and etching a plurality ofisolation trenches through the plurality of light absorbing layers intosaid semiconductor substrate.
 2. The photolithographic method of claim1, wherein each layer of the light absorbing layers is between 100 and400 Å thick.
 3. The photolithographic method of claim 1, wherein eachlayer of the light absorbing layers is 250 Å thick.
 4. Thephotolithographic method of claim 1, wherein the light absorbing layersconsists of three layers in which two of the three layers is formed ofSiON and one of the three layers is formed of SiO₂.
 5. Thephotolithographic method of claim 1, wherein a barrier oxide layer isformed over the semiconductor substrate, and the plurality of lightabsorbing layers are formed over the barrier oxide layer.
 6. Thephotolithographic method of claim 5, wherein the light absorbing layersare formed directly on the barrier oxide layer.
 7. The photolithographicmethod of claim 1, wherein the semiconductor substrate comprises Si. 8.The photolithographic method of claim 1, wherein during the patterning,light which is reflected by the semiconductor substrate and othermaterial is substantially absorbed by the plurality of light absorbinglayers.
 9. A photolithographic method for forming isolation trenches,comprising the steps of: forming a plurality of light absorbing layershaving a combined extinction coefficient >0.5 over a semiconductorsubstrate, the light absorbing layers comprising a layer of SiO₂ betweentwo layers of SiON, and each layer of the light absorbing layers havinga thickness between 100 and 400 Å; patterning a photoresist over theplurality of light absorbing layers; and etching a plurality ofisolation trenches through the plurality of light absorbing layers intosaid semiconductor substrate.
 10. The photolithographic method of claim9, wherein each layer of the light absorbing layers is 250 Å thick. 11.The photolithographic method of claim 9, wherein a barrier oxide layeris formed over the semiconductor substrate, and the plurality of lightabsorbing layers are formed over the barrier oxide layer.
 12. Thephotolithographic method of claim 11, wherein the light absorbing layersare formed directly on the barrier oxide layer.
 13. Thephotolithographic method of claim 9, wherein the semiconductor substratecomprises Si.
 14. The photolithographic method of claim 9, whereinduring the patterning, light which is reflected by the semiconductorsubstrate and other material is substantially absorbed by the pluralityof light absorbing layers.
 15. A photolithographic method for formingisolation trenches, comprising the steps of: forming a barrier oxidelayer over a semiconductor substrate, the semiconductor substratecomprising silicon; forming a plurality of light absorbing layers havinga combined extinction coefficient >0.5 over the barrier oxide layer, thelight absorbing layers alternating between a layer of SiON and a layerof SiO₂, and each layer of the light absorbing layers having a thicknessbetween 100 and 400 Å patterning a photoresist over the plurality oflight absorbing layers; and etching a plurality of isolation trenchesthrough the plurality of light absorbing layers and the barrier oxidelayer into said semiconductor substrate.
 16. The photolithographicmethod of claim 14, wherein the light absorbing layers are formeddirectly on the barrier oxide layer.
 17. The photolithographic method ofclaim 14, wherein during the patterning, light which is reflected by thesemiconductor substrate and other material is substantially absorbed bythe plurality of light absorbing layers.
 18. The photolithographicmethod of claim 14, wherein each layer of the light absorbing layers is250 Å thick.